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Add lifting for vector comparisons, bitwise operations, widening and narrowing moves, multiply-long, negation, pairwise addition, shifts, swaps, transposes, tests, and interleaving operations. Use dedicated intrinsics for lane-wise operations and explicit IL for bitwise operations, register swaps, and scalar floating-point negation. Correct SIMD decoding, signedness, immediate types, D/Q operand widths, and reserved encodings. Support ARMv8 VMULL.P64 polynomial products. Add FLDMDBX/FLDMIAX and FSTMDBX/FSTMIAX lifting, accounting for the unused trailing word in addressing and writeback. Correct Thumb decoding of these forms, including SP-based transfers.
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This PR expands lifting for vector comparisons, bitwise operations, widening/narrowing moves, and more. Expansion includes all the ARMv7 instructions from this issue: https://github.com/Vector35/binaryninja/issues/1910
In addition to expanding lifting, I had to make fixes to the thumb-2 decoder. Here is a short summary:
vorr/vbic/vmvnimmediates: derive.i16/.i32types fromcmodeinstead of register bits, immediate payload bits, or a constantvmovl: preserve the encoded signedness instead of unconditionally marking all widening moves as unsignedvcge #0: include the F bit when selecting the data type so.f32is distinguished from.s32vmull.p64: add the ARMv8 polynomial-multiple decodingfldm*x/fstm*xencodings before selectingvpop/vpushaliasesI've uploaded my test binaries that I used for verification in addition to the binaries in this repository: https://github.com/Aarno-Labs/iot-binary-dataset (that are responsible for uncovering the issues)
armv7-dh-lifting-expansion.zip
Before:
After: