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[ARMv7] Expand ARM, Thumb, and NEON lifting coverage
Add LLIL support for a broad set of previously unimplemented or partially implemented ARMv7, Thumb2, VFP, and NEON instructions. Cover system, control, synchronization, hint, and coprocessor operations, including MRS, MSR, VMSR, VMRS, SMC, HVC, CPS/CPSID/CPSIE, CLREX, DMB, DSB, ISB, PLD, SETEND, SRS/RFE, STC/LDC variants, and related intrinsics. Add integer, DSP, saturation, CRC, multiply, and packed arithmetic lifting, including CRC32 variants, QADD/QSUB forms, SSAT/USAT forms, SMMUL/SMMLA, SMLA/SMLAL variants, SXT/UXT variants, REV/RBIT/SEL, packed add/sub variants, UQASX/UQSAX, and Thumb writeback/control-transfer cases. Expand VFP/NEON support for vector moves, arithmetic, comparisons, conversions, shifts, narrowing/widening operations, structured loads/stores, table lookup, reductions, duplicate/reverse/ext operations, and fused multiply forms, wiring new intrinsics and metadata where needed. Extend ARM/Thumb decoder support where required, including CRC32 Thumb variants, and add focused ARM and Thumb lift tests for the new coverage.
1 parent 5a7ab29 commit f5ebdef

9 files changed

Lines changed: 8887 additions & 2954 deletions

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‎arch/armv7/arch_armv7.cpp‎

Lines changed: 1203 additions & 7 deletions
Large diffs are not rendered by default.

‎arch/armv7/armv7_disasm/armv7.c‎

Lines changed: 36 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,32 @@ static Register regMap[2] = {REG_D0, REG_Q0};
4848
#define SET_REGISTER(x) (1<<((x)))
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#define DECODE_DT(s,u) (enum DataType)(1+((((u&1))<<2) | ((s)&3)))
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static uint32_t armv7_crc32(uint32_t instructionValue, Instruction* restrict instruction)
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{
53+
if ((instructionValue & 0x0f900df0) != 0x01000040)
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return 1;
55+
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uint32_t size = (instructionValue >> 21) & 3;
57+
uint32_t castagnoli = (instructionValue >> 9) & 1;
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if (size == 3)
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return 1;
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static Operation crc32Operation[2][3] = {
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{ ARMV7_CRC32B, ARMV7_CRC32H, ARMV7_CRC32W },
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{ ARMV7_CRC32CB, ARMV7_CRC32CH, ARMV7_CRC32CW },
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};
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instruction->operation = crc32Operation[castagnoli][size];
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instruction->cond = (enum Condition)(instructionValue >> 28);
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instruction->operands[0].cls = REG;
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instruction->operands[0].reg = (enum Register)((instructionValue >> 12) & 0xf);
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instruction->operands[1].cls = REG;
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instruction->operands[1].reg = (enum Register)((instructionValue >> 16) & 0xf);
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instruction->operands[2].cls = REG;
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instruction->operands[2].reg = (enum Register)(instructionValue & 0xf);
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return 0;
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}
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static const char* operationString[] = {
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"UNDEFINED",
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"UNPREDICTABLE",
@@ -77,6 +103,12 @@ static const char* operationString[] = {
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"cdp2",
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"clrex",
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"clz",
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"crc32b",
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"crc32cb",
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"crc32ch",
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"crc32cw",
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"crc32h",
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"crc32w",
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"cmn",
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"cmp",
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"cps",
@@ -1081,6 +1113,9 @@ uint32_t armv7_data_processing_and_misc(uint32_t instructionValue, Instruction*
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} decode;
10821114

10831115
decode.value = instructionValue;
1116+
if (armv7_crc32(instructionValue, instruction) == 0)
1117+
return 0;
1118+
10841119
if (decode.op == 0)
10851120
{
10861121
if ((decode.op1 & 0x19) == 0x10) //10xx0
@@ -4443,9 +4478,7 @@ uint32_t armv7_simd_data_processing(uint32_t instructionValue, Instruction* rest
44434478
instruction->operands[2].cls = REG;
44444479
instruction->operands[2].reg = (Register)(regMap[decode.vext.q] + ((decode.vext.m << 4 | decode.vext.vm) >> decode.vext.q));
44454480
instruction->operands[3].cls = IMM;
4446-
instruction->operands[3].imm = decode.vext.imm4 * 8;
4447-
if (decode.vext.q)
4448-
instruction->operands[3].imm <<= 1;
4481+
instruction->operands[3].imm = decode.vext.imm4;
44494482
}
44504483
else if (decode.com.b <= 7)
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{

‎arch/armv7/armv7_disasm/armv7.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,12 @@ enum Operation {
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ARMV7_CDP2,
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ARMV7_CLREX,
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ARMV7_CLZ,
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ARMV7_CRC32B,
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ARMV7_CRC32CB,
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ARMV7_CRC32CH,
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ARMV7_CRC32CW,
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ARMV7_CRC32H,
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ARMV7_CRC32W,
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ARMV7_CMN,
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ARMV7_CMP,
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ARMV7_CPS,

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