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Add ARMv7 vabs and fix vcvt lifting
Lift scalar VABS directly when the lane and register widths match, and use intrinsics for packed ARM and Thumb forms Correct Thumb F32/F64 VCVT result sizing, fix scalar fixed-point rounding and extension, and add an intrinsic for lane-wise fixed-point conversions
1 parent 34d12c3 commit 25782a7

6 files changed

Lines changed: 319 additions & 65 deletions

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‎arch/armv7/arch_armv7.cpp‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1601,6 +1601,14 @@ class Armv7Architecture: public ArmCommonArchitecture
16011601
return "__vrhadd";
16021602
case ARMV7_INTRIN_VRECPE:
16031603
return "__vrecpe";
1604+
case ARMV7_INTRIN_VABS:
1605+
return "__vabs";
1606+
case ARMV7_INTRIN_VCVT_FIXED:
1607+
return "__vcvt_fixed";
1608+
case ARMV7_INTRIN_VABS_Q:
1609+
return "__vabs_q";
1610+
case ARMV7_INTRIN_VCVT_FIXED_Q:
1611+
return "__vcvt_fixed_q";
16041612
case ARMV7_INTRIN_VQSHL:
16051613
return "__vqshl";
16061614
case ARMV7_INTRIN_VQRSHL:
@@ -1866,6 +1874,10 @@ class Armv7Architecture: public ArmCommonArchitecture
18661874
ARMV7_INTRIN_VHADD,
18671875
ARMV7_INTRIN_VRHADD,
18681876
ARMV7_INTRIN_VRECPE,
1877+
ARMV7_INTRIN_VABS,
1878+
ARMV7_INTRIN_VCVT_FIXED,
1879+
ARMV7_INTRIN_VABS_Q,
1880+
ARMV7_INTRIN_VCVT_FIXED_Q,
18691881
ARMV7_INTRIN_VQSHL,
18701882
ARMV7_INTRIN_VQRSHL,
18711883
ARMV7_INTRIN_VQSHRN,
@@ -2196,10 +2208,23 @@ class Armv7Architecture: public ArmCommonArchitecture
21962208
NameAndType("source2", Type::IntegerType(8, false)),
21972209
};
21982210
case ARMV7_INTRIN_VRECPE:
2211+
case ARMV7_INTRIN_VABS:
2212+
case ARMV7_INTRIN_VABS_Q:
21992213
return {
22002214
NameAndType("size", Type::IntegerType(1, false)),
22012215
NameAndType("is_float", Type::BoolType()),
2202-
NameAndType("source", Type::IntegerType(8, false)),
2216+
NameAndType("source", Type::IntegerType(
2217+
intrinsic == ARMV7_INTRIN_VABS_Q ? 16 : 8, false)),
2218+
};
2219+
case ARMV7_INTRIN_VCVT_FIXED:
2220+
case ARMV7_INTRIN_VCVT_FIXED_Q:
2221+
return {
2222+
NameAndType("size", Type::IntegerType(1, false)),
2223+
NameAndType("fractional_bits", Type::IntegerType(1, false)),
2224+
NameAndType("to_fixed", Type::BoolType()),
2225+
NameAndType("is_unsigned", Type::BoolType()),
2226+
NameAndType("source", Type::IntegerType(
2227+
intrinsic == ARMV7_INTRIN_VCVT_FIXED_Q ? 16 : 8, false)),
22032228
};
22042229
case ARMV7_INTRIN_VREV16:
22052230
case ARMV7_INTRIN_VREV32:
@@ -2550,6 +2575,8 @@ class Armv7Architecture: public ArmCommonArchitecture
25502575
case ARMV7_INTRIN_VHADD:
25512576
case ARMV7_INTRIN_VRHADD:
25522577
case ARMV7_INTRIN_VRECPE:
2578+
case ARMV7_INTRIN_VABS:
2579+
case ARMV7_INTRIN_VCVT_FIXED:
25532580
case ARMV7_INTRIN_VQSHL:
25542581
case ARMV7_INTRIN_VQRSHL:
25552582
case ARMV7_INTRIN_VQSHRN:
@@ -2565,6 +2592,9 @@ class Armv7Architecture: public ArmCommonArchitecture
25652592
case ARMV7_INTRIN_VBIT:
25662593
case ARMV7_INTRIN_VBSL:
25672594
return { Type::IntegerType(8, false) };
2595+
case ARMV7_INTRIN_VABS_Q:
2596+
case ARMV7_INTRIN_VCVT_FIXED_Q:
2597+
return { Type::IntegerType(16, false) };
25682598
case ARMV7_INTRIN_VABAL:
25692599
case ARMV7_INTRIN_VABDL:
25702600
case ARMV7_INTRIN_VADDL:

‎arch/armv7/il.cpp‎

Lines changed: 108 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -4542,64 +4542,76 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI
45424542
if (op3.cls == IMM)
45434543
{
45444544
size_t destSize = get_register_size(op1.reg);
4545-
size_t fixedSize = GetDataTypeSize(instr.dataType);
4546-
if (!fixedSize)
4547-
fixedSize = destSize;
4548-
size_t sourceSize = GetDataTypeSize(instr.dataType2);
4549-
if (!sourceSize)
4550-
sourceSize = get_register_size(op2.reg);
4551-
auto source = [&]() {
4552-
ExprId value = il.Register(get_register_size(op2.reg), op2.reg);
4553-
if (sourceSize < get_register_size(op2.reg))
4554-
value = il.LowPart(sourceSize, value);
4555-
return value;
4556-
};
4557-
switch (instr.dataType)
4545+
size_t sourceRegisterSize = get_register_size(op2.reg);
4546+
bool destIsFloat = instr.dataType == DT_F32 || instr.dataType == DT_F64;
4547+
bool sourceIsFloat = instr.dataType2 == DT_F32 || instr.dataType2 == DT_F64;
4548+
bool toFixed = !destIsFloat && sourceIsFloat;
4549+
bool fromFixed = destIsFloat && !sourceIsFloat;
4550+
DataType fixedType = toFixed ? instr.dataType : instr.dataType2;
4551+
DataType floatType = toFixed ? instr.dataType2 : instr.dataType;
4552+
size_t fixedSize = GetDataTypeSize(fixedType);
4553+
size_t floatSize = GetDataTypeSize(floatType);
4554+
bool validFixedType = fixedType == DT_S16 || fixedType == DT_U16
4555+
|| fixedType == DT_S32 || fixedType == DT_U32;
4556+
bool isUnsigned = fixedType == DT_U16 || fixedType == DT_U32;
4557+
4558+
if ((!toFixed && !fromFixed) || !validFixedType || fixedSize == 0 || floatSize == 0
4559+
|| destSize == 0 || sourceRegisterSize == 0 || destSize != sourceRegisterSize)
45584560
{
4559-
case DT_S16:
4560-
case DT_S32:
4561-
ConditionExecute(il, instr.cond, il.SetRegister(destSize, op1.reg,
4562-
il.SignExtend(destSize,
4563-
il.FloatToInt(fixedSize,
4564-
il.RoundToInt(sourceSize,
4565-
il.FloatMult(sourceSize,
4566-
source(),
4567-
FixedPointScale(il, sourceSize, op3.imm)))))));
4568-
break;
4569-
case DT_U16:
4570-
case DT_U32:
4571-
ConditionExecute(il, instr.cond, il.SetRegister(destSize, op1.reg,
4572-
il.ZeroExtend(destSize,
4573-
il.FloatToInt(fixedSize,
4574-
il.RoundToInt(sourceSize,
4575-
il.FloatMult(sourceSize,
4576-
source(),
4577-
FixedPointScale(il, sourceSize, op3.imm)))))));
4561+
ConditionExecute(il, instr.cond, il.Unimplemented());
45784562
break;
4579-
case DT_F32:
4580-
case DT_F64:
4581-
switch (instr.dataType2)
4563+
}
4564+
4565+
if (destSize != floatSize)
4566+
{
4567+
if (floatSize != 4 || fixedSize != 4 || (destSize != 8 && destSize != 16))
45824568
{
4583-
case DT_S16:
4584-
case DT_S32:
4585-
ConditionExecute(il, instr.cond, il.SetRegister(destSize, op1.reg,
4586-
il.FloatDiv(destSize,
4587-
il.IntToFloat(destSize, il.SignExtend(destSize, source())),
4588-
FixedPointScale(il, destSize, op3.imm))));
4589-
break;
4590-
case DT_U16:
4591-
case DT_U32:
4592-
ConditionExecute(il, instr.cond, il.SetRegister(destSize, op1.reg,
4593-
il.FloatDiv(destSize,
4594-
il.IntToFloat(destSize, il.ZeroExtend(destSize, source())),
4595-
FixedPointScale(il, destSize, op3.imm))));
4596-
break;
4597-
default:
4569+
ConditionExecute(il, instr.cond, il.Unimplemented());
45984570
break;
45994571
}
4572+
4573+
ConditionExecute(il, instr.cond,
4574+
il.Intrinsic(
4575+
{ RegisterOrFlag::Register(op1.reg) },
4576+
destSize == 16 ? ARMV7_INTRIN_VCVT_FIXED_Q : ARMV7_INTRIN_VCVT_FIXED,
4577+
{
4578+
il.Const(1, floatSize * 8),
4579+
il.Const(1, op3.imm),
4580+
il.Const(1, toFixed ? 1 : 0),
4581+
il.Const(1, isUnsigned ? 1 : 0),
4582+
il.Register(sourceRegisterSize, op2.reg),
4583+
}));
46004584
break;
4601-
default:
4602-
break;
4585+
}
4586+
4587+
if (toFixed)
4588+
{
4589+
ExprId scaled = il.FloatMult(floatSize,
4590+
il.Register(sourceRegisterSize, op2.reg),
4591+
FixedPointScale(il, floatSize, op3.imm));
4592+
// LLIL_FLOAT_TO_INT is signed. Use the next wider integer size for unsigned
4593+
// conversions so values in the upper half of the fixed-point range do not
4594+
// overflow before they are zero-extended.
4595+
size_t conversionSize = isUnsigned ? fixedSize * 2 : fixedSize;
4596+
ExprId converted = il.FloatToInt(conversionSize, il.FloatTrunc(floatSize, scaled));
4597+
if (conversionSize > fixedSize)
4598+
converted = il.LowPart(fixedSize, converted);
4599+
converted = isUnsigned
4600+
? il.ZeroExtend(destSize, converted)
4601+
: il.SignExtend(destSize, converted);
4602+
ConditionExecute(il, instr.cond, il.SetRegister(destSize, op1.reg, converted));
4603+
}
4604+
else
4605+
{
4606+
ExprId source = il.Register(sourceRegisterSize, op2.reg);
4607+
if (fixedSize < sourceRegisterSize)
4608+
source = il.LowPart(fixedSize, source);
4609+
ExprId converted = isUnsigned
4610+
? il.IntToFloat(floatSize, il.ZeroExtend(floatSize, source))
4611+
: il.IntToFloat(floatSize, il.SignExtend(floatSize, source));
4612+
ConditionExecute(il, instr.cond,
4613+
il.SetRegister(destSize, op1.reg,
4614+
il.FloatDiv(floatSize, converted, FixedPointScale(il, floatSize, op3.imm))));
46034615
}
46044616
break;
46054617
}
@@ -4651,6 +4663,12 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI
46514663
il.ZeroExtend(get_register_size(op1.reg),
46524664
il.Register(get_register_size(op2.reg), op2.reg)))));
46534665
break;
4666+
case DT_F32:
4667+
case DT_F64:
4668+
ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg,
4669+
il.FloatConvert(get_register_size(op1.reg),
4670+
il.Register(get_register_size(op2.reg), op2.reg))));
4671+
break;
46544672
default:
46554673
break;
46564674
}
@@ -4659,6 +4677,44 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI
46594677
break;
46604678
}
46614679
break;
4680+
case ARMV7_VABS:
4681+
if (op1.cls != REG || op2.cls != REG || op3.cls != NONE)
4682+
{
4683+
ConditionExecute(il, instr.cond, il.Unimplemented());
4684+
break;
4685+
}
4686+
4687+
{
4688+
size_t elementSize = GetDataTypeSize(instr.dataType);
4689+
size_t destSize = get_register_size(op1.reg);
4690+
size_t sourceSize = get_register_size(op2.reg);
4691+
bool isFloat = (instr.dataType == DT_F32) || (instr.dataType == DT_F64);
4692+
if (elementSize == 0 || destSize == 0 || sourceSize == 0 || destSize != sourceSize)
4693+
{
4694+
ConditionExecute(il, instr.cond, il.Unimplemented());
4695+
break;
4696+
}
4697+
4698+
if (isFloat && elementSize == destSize)
4699+
{
4700+
ConditionExecute(il, instr.cond,
4701+
il.SetRegister(destSize, op1.reg,
4702+
il.FloatAbs(destSize, il.Register(sourceSize, op2.reg))));
4703+
}
4704+
else
4705+
{
4706+
ConditionExecute(il, instr.cond,
4707+
il.Intrinsic(
4708+
{ RegisterOrFlag::Register(op1.reg) },
4709+
destSize == 16 ? ARMV7_INTRIN_VABS_Q : ARMV7_INTRIN_VABS,
4710+
{
4711+
il.Const(1, elementSize * 8),
4712+
il.Const(1, isFloat ? 1 : 0),
4713+
il.Register(sourceSize, op2.reg),
4714+
}));
4715+
}
4716+
}
4717+
break;
46624718
case ARMV7_VADD:
46634719
if (op1.cls != REG || op2.cls != REG || op3.cls != REG)
46644720
{

‎arch/armv7/il.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,10 @@ enum Armv7Intrinsic : uint32_t
201201
ARMV7_INTRIN_VSUB,
202202
ARMV7_INTRIN_VRHADD,
203203
ARMV7_INTRIN_VRECPE,
204+
ARMV7_INTRIN_VABS,
205+
ARMV7_INTRIN_VCVT_FIXED,
206+
ARMV7_INTRIN_VABS_Q,
207+
ARMV7_INTRIN_VCVT_FIXED_Q,
204208
};
205209

206210
enum ArmFakeRegister: uint32_t

‎arch/armv7/test_lift.py‎

Lines changed: 67 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,15 @@ def vector_unary_intrinsic_expected(dst, intrinsic, size, modifier, src):
1919
src_size = 'o' if src.startswith('q') else 'q'
2020
return f'LLIL_INTRINSIC([{dst}],__{intrinsic},[LLIL_CONST.b(0x{size:X}),LLIL_CONST.b(0x{modifier:X}),LLIL_REG.{src_size}({src})])'
2121

22+
def vector_fixed_convert_intrinsic_expected(dst, size, fractional_bits, to_fixed, unsigned, src):
23+
src_size = 'o' if src.startswith('q') else 'q'
24+
intrinsic = 'vcvt_fixed_q' if dst.startswith('q') else 'vcvt_fixed'
25+
return (
26+
f'LLIL_INTRINSIC([{dst}],__{intrinsic},[LLIL_CONST.b(0x{size:X}),'
27+
f'LLIL_CONST.b(0x{fractional_bits:X}),LLIL_CONST.b(0x{to_fixed:X}),'
28+
f'LLIL_CONST.b(0x{unsigned:X}),LLIL_REG.{src_size}({src})])'
29+
)
30+
2231
def saturating_scalar_expected(dst, src1, src2, intrinsic):
2332
return scalar_q_intrinsic_expected(dst, intrinsic, src1, src2)
2433

@@ -652,6 +661,26 @@ def vmlal_expected(size, unsigned):
652661
('A', b'\x44\xa4\xfb\xf3', vector_unary_intrinsic_expected('q13', 'vrecpe', 32, 0, 'q2')),
653662
# vrecpe.u32 q13, q2
654663
('T', b'\xfb\xff\x44\xa4', vector_unary_intrinsic_expected('q13', 'vrecpe', 32, 0, 'q2')),
664+
# vabs.f32 s0, s1
665+
('A', b'\xe0\x0a\xb0\xee', 'LLIL_SET_REG.d(s0,LLIL_FABS.d(LLIL_REG.d(s1)))'),
666+
# vabs.f64 d1, d2
667+
('A', b'\xc2\x1b\xb0\xee', 'LLIL_SET_REG.q(d1,LLIL_FABS.q(LLIL_REG.q(d2)))'),
668+
# vabs.f32 d0, d1
669+
('A', b'\x01\x07\xb9\xf3', vector_unary_intrinsic_expected('d0', 'vabs', 32, 1, 'd1')),
670+
# vabs.f32 q1, q2
671+
('A', b'\x44\x27\xb9\xf3', vector_unary_intrinsic_expected('q1', 'vabs_q', 32, 1, 'q2')),
672+
# vabs.s16 d0, d1
673+
('A', b'\x01\x03\xb5\xf3', vector_unary_intrinsic_expected('d0', 'vabs', 16, 0, 'd1')),
674+
# vabs.f32 s0, s1
675+
('T', b'\xb0\xee\xe0\x0a', 'LLIL_SET_REG.d(s0,LLIL_FABS.d(LLIL_REG.d(s1)))'),
676+
# vabs.f64 d1, d2
677+
('T', b'\xb0\xee\xc2\x1b', 'LLIL_SET_REG.q(d1,LLIL_FABS.q(LLIL_REG.q(d2)))'),
678+
# vabs.f32 d0, d1
679+
('T', b'\xb9\xff\x01\x07', vector_unary_intrinsic_expected('d0', 'vabs', 32, 1, 'd1')),
680+
# vabs.f32 q1, q2
681+
('T', b'\xb9\xff\x44\x27', vector_unary_intrinsic_expected('q1', 'vabs_q', 32, 1, 'q2')),
682+
# vabs.s16 d0, d1
683+
('T', b'\xb5\xff\x01\x03', vector_unary_intrinsic_expected('d0', 'vabs', 16, 0, 'd1')),
655684
# vceq.s16 d16, d0, d13
656685
('T', b'\x50\xff\x1d\x08', vector_intrinsic_expected('d16', 'vceq', 16, 0, 'd0', 'd13')),
657686
# vcgt.s32 d0, d19, #0
@@ -692,10 +721,46 @@ def vmlal_expected(size, unsigned):
692721
('T', b'\xba\xee\xef\x7a', 'LLIL_SET_REG.d(s14,LLIL_FDIV.d(LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(s14))),LLIL_FLOAT_CONST.d(2.0)))'),
693722
# vcvt.f64.u32 d7, d7, #1
694723
('T', b'\xbb\xee\xef\x7b', 'LLIL_SET_REG.q(d7,LLIL_FDIV.q(LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_LOW_PART.d(LLIL_REG.q(d7)))),LLIL_FLOAT_CONST.q(2.0)))'),
724+
# vcvt.s16.f32 s0, s0, #8
725+
('A', b'\x44\x0a\xbe\xee', 'LLIL_SET_REG.d(s0,LLIL_SX.d(LLIL_FLOAT_TO_INT.w(LLIL_FTRUNC.d(LLIL_FMUL.d(LLIL_REG.d(s0),LLIL_FLOAT_CONST.d(256.0))))))'),
726+
# vcvt.f32.s16 s1, s1, #8
727+
('A', b'\x44\x0a\xfa\xee', 'LLIL_SET_REG.d(s1,LLIL_FDIV.d(LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_LOW_PART.w(LLIL_REG.d(s1)))),LLIL_FLOAT_CONST.d(256.0)))'),
728+
# vcvt.u16.f64 d2, d2, #12
729+
('T', b'\xbf\xee\x42\x2b', 'LLIL_SET_REG.q(d2,LLIL_ZX.q(LLIL_LOW_PART.w(LLIL_FLOAT_TO_INT.d(LLIL_FTRUNC.q(LLIL_FMUL.q(LLIL_REG.q(d2),LLIL_FLOAT_CONST.q(4096.0)))))))'),
730+
# vcvt.f64.u16 d3, d3, #12
731+
('T', b'\xbb\xee\x42\x3b', 'LLIL_SET_REG.q(d3,LLIL_FDIV.q(LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_LOW_PART.w(LLIL_REG.q(d3)))),LLIL_FLOAT_CONST.q(4096.0)))'),
732+
# vcvt.u16.f32 s0, s0, #16
733+
('A', b'\x40\x0a\xbf\xee', 'LLIL_SET_REG.d(s0,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_FLOAT_TO_INT.d(LLIL_FTRUNC.d(LLIL_FMUL.d(LLIL_REG.d(s0),LLIL_FLOAT_CONST.d(65536.0)))))))'),
734+
# vcvt.u16.f32 s0, s0, #16
735+
('T', b'\xbf\xee\x40\x0a', 'LLIL_SET_REG.d(s0,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_FLOAT_TO_INT.d(LLIL_FTRUNC.d(LLIL_FMUL.d(LLIL_REG.d(s0),LLIL_FLOAT_CONST.d(65536.0)))))))'),
736+
# vcvt.u32.f32 s0, s0, #32
737+
('A', b'\xc0\x0a\xbf\xee', 'LLIL_SET_REG.d(s0,LLIL_ZX.d(LLIL_LOW_PART.d(LLIL_FLOAT_TO_INT.q(LLIL_FTRUNC.d(LLIL_FMUL.d(LLIL_REG.d(s0),LLIL_FLOAT_CONST.d(4294967296.0)))))))'),
738+
# vcvt.u32.f32 s0, s0, #32
739+
('T', b'\xbf\xee\xc0\x0a', 'LLIL_SET_REG.d(s0,LLIL_ZX.d(LLIL_LOW_PART.d(LLIL_FLOAT_TO_INT.q(LLIL_FTRUNC.d(LLIL_FMUL.d(LLIL_REG.d(s0),LLIL_FLOAT_CONST.d(4294967296.0)))))))'),
740+
# vcvt.s32.f32 d0, d1, #16
741+
('A', b'\x11\x0f\xb0\xf2', vector_fixed_convert_intrinsic_expected('d0', 32, 16, 1, 0, 'd1')),
742+
# vcvt.u32.f32 q1, q2, #8
743+
('A', b'\x54\x2f\xb8\xf3', vector_fixed_convert_intrinsic_expected('q1', 32, 8, 1, 1, 'q2')),
744+
# vcvt.f32.s32 d2, d3, #16
745+
('A', b'\x13\x2e\xb0\xf2', vector_fixed_convert_intrinsic_expected('d2', 32, 16, 0, 0, 'd3')),
746+
# vcvt.f32.u32 q3, q4, #8
747+
('A', b'\x58\x6e\xb8\xf3', vector_fixed_convert_intrinsic_expected('q3', 32, 8, 0, 1, 'q4')),
748+
# vcvt.s32.f32 d0, d1, #16
749+
('T', b'\xb0\xef\x11\x0f', vector_fixed_convert_intrinsic_expected('d0', 32, 16, 1, 0, 'd1')),
750+
# vcvt.u32.f32 q1, q2, #8
751+
('T', b'\xb8\xff\x54\x2f', vector_fixed_convert_intrinsic_expected('q1', 32, 8, 1, 1, 'q2')),
752+
# vcvt.f32.s32 d2, d3, #16
753+
('T', b'\xb0\xef\x13\x2e', vector_fixed_convert_intrinsic_expected('d2', 32, 16, 0, 0, 'd3')),
754+
# vcvt.f32.u32 q3, q4, #8
755+
('T', b'\xb8\xff\x58\x6e', vector_fixed_convert_intrinsic_expected('q3', 32, 8, 0, 1, 'q4')),
756+
# vcvt.f64.f32 d3, s4
757+
('T', b'\xb7\xee\xc2\x3a', 'LLIL_SET_REG.q(d3,LLIL_FLOAT_CONV.q(LLIL_REG.d(s4)))'),
758+
# vcvt.f32.f64 s5, d4
759+
('T', b'\xf7\xee\xc4\x2b', 'LLIL_SET_REG.d(s5,LLIL_FLOAT_CONV.d(LLIL_REG.q(d4)))'),
695760
# vcvt.s32.f64 d2, d2, #0x20
696-
('A', b'\xc0\x2b\xbe\xee', 'LLIL_SET_REG.q(d2,LLIL_SX.q(LLIL_FLOAT_TO_INT.d(LLIL_ROUND_TO_INT.q(LLIL_FMUL.q(LLIL_REG.q(d2),LLIL_FLOAT_CONST.q(4294967296.0))))))'),
761+
('A', b'\xc0\x2b\xbe\xee', 'LLIL_SET_REG.q(d2,LLIL_SX.q(LLIL_FLOAT_TO_INT.d(LLIL_FTRUNC.q(LLIL_FMUL.q(LLIL_REG.q(d2),LLIL_FLOAT_CONST.q(4294967296.0))))))'),
697762
# vcvt.u32.f64 d20, d20, #0x20
698-
('A', b'\xc0\x4b\xff\xee', 'LLIL_SET_REG.q(d20,LLIL_ZX.q(LLIL_FLOAT_TO_INT.d(LLIL_ROUND_TO_INT.q(LLIL_FMUL.q(LLIL_REG.q(d20),LLIL_FLOAT_CONST.q(4294967296.0))))))'),
763+
('A', b'\xc0\x4b\xff\xee', 'LLIL_SET_REG.q(d20,LLIL_ZX.q(LLIL_LOW_PART.d(LLIL_FLOAT_TO_INT.q(LLIL_FTRUNC.q(LLIL_FMUL.q(LLIL_REG.q(d20),LLIL_FLOAT_CONST.q(4294967296.0)))))))'),
699764
# vmaxnm.f64 d11, d11, d7
700765
('T', b'\x8b\xfe\x07\xbb', 'LLIL_INTRINSIC([d11],__vmaxnm,[LLIL_REG.q(d11),LLIL_REG.q(d7)])'),
701766
# vminnm.f64 d8, d8, d9

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