convert gray to bcd and vice versa using verilog
you can test project with test module file
study about gray code at https://en.wikipedia.org/wiki/Gray_code
| Name | Name | Last commit date | ||
|---|---|---|---|---|
convert gray to bcd and vice versa using verilog
you can test project with test module file
study about gray code at https://en.wikipedia.org/wiki/Gray_code