Update RISC-V Demo for Spike simulator - #1415

Description

Some commands in the Makefile and OpenOCD config file had to be updated to work with the current OpenOCD and RISC-V toolchain.

Makefile:

• Zicsr is now a standalone extension, so update the value of the -march argument, passed to GCC.

spike-1.cfg for OpenOCD:

• Update commands that changed their syntax - avoid deprecation warnings.
• Remove "adapter_khz" command - the virtual jtag_vpi adapter does not have any concept of clock frequency.
• Update -expected-id to match the JTAG IDCODE used by the Spike simulator.
• Fix the syntax of the "expr" command.
• Remove the command that zeroes mstatus register upon startup, as this would break the program operation. It is unclear why the command was there in the first place.

Test Steps

• Build Spike RISC-V ISA simulator from source (https://github.com/riscv-software-src/riscv-isa-sim).
• Build OpenOCD from source (https://github.com/openocd-org/openocd).
• Download RISC-V bare-metal toolchain from https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/blog/2025/10/23/riscv-none-elf-gcc-v15-2-0-1-released/.
• Build the demo:
  • cd FreeRTOS/Demo/RISC-V-spike-htif_GCC
  • PATH=/path/to/your/xpack-riscv-none-elf-gcc-15.2.0-1/bin:$PATH make CROSS=riscv-none-elf- DEBUG=1
• Launch the Spike simulator:
  • /path/to/your/bin/spike -p1 --isa rv32ima_zicsr -m0x80000000:0x10000000 --rbb-port 9824 build/RTOSDemo32.axf
• In another terminal, launch OpenOCD:
  • /path/to/your/bin/openocd -f spike-1.cfg
• Check for successful target examination in the OpenOCD log:

...
Info : [riscv.cpu] Examined RISC-V core
Info : [riscv.cpu]  XLEN=32, misa=0x40141101
Info : [riscv.cpu] Examination succeed
Info : [riscv.cpu] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
...

Checklist:

• I have tested my changes. No regression in existing tests.
• I have modified and/or added unit-tests to cover the code changes in this Pull Request.

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